1. Import of the layout data

   Import the stream file (LED.str or LED.gds) into the layout editor.

   1. Menu of CIW: File > Import > Stream...
   2. Click the Show Options button.

      

      Stream File	ICC/LED.str (was output from IC compiler)
      Destination Library	Lticka
      Load ASCII Tech File	rohm180technology_ic6.tf（Technology file of Cadence IC tools）
      Overwrite Existing Cells	Untick
      Label Case Sensitivity	Preserve

   3. Click the Translate button.
      Confirm no error on the PopUp Message, and click OK button. Ignore the warning. If you find the error message, click "Display Log" and check the description about the error.

2. Creating a layout view
   1. Menu of Library Manager: File > New > Cell View...
   2. Create the cell named top_led.
      Layout XL has a function of the netlist-driven layout, but Layout L do not have it. In this design, we will make the layout without the schematic or netlist of the circuit, and Layout L is employed to design the layout. You can also use Layout XL for this practice.

      

   3. The top_led is added in Library Manager and start the layout editor

3. Connection of the rosc to the LED
   1. Bring up LED and rosc on the layout editor by pressing i-key. You can exit from the instance mode by ESC key.
   2. Connect the VDD!, VSS!, OSC_CLK and CLK.
      • The CLK of LED cell terminated on the METAL5 layer. On the other hand, The OSC_CLK of rsoc terminated on the METAL2 layer. Thus, the CLK and OSC_CLK have tobe connected through METAL5-VIA4-METAL4-VIA3-METAL3-VIA2-METAL2.
      • There is no label of the wiring in the LED cell. The outside power-ring is VDD! and the inside power-ring is VSS!.
        You can discriminate the VDD! from VSS! by checking the layout in the standard cells. The VDD! has a connection to NWELL.

      

   3. Save the top_led

4. DRC of the core circuit

The semiconductor manufacturer accepts the design data with the GDS-II format. GDS-II data also called stream data. The stream data is usually exported after the design of top-level cell including a frame and IO buffers. In this project, export each core separately to merge the core data designed by other participants.

1. Menu of CIW: File > Export > Stream...
2. Input the file name of the destination in the input box of Stream File.
   Use the file name including your name to distinguish your data and others.
   Use the file extension of .gds.
3. Click "..." button of the right hand side of the input box of Library and choose the layout data to export.
   For example: Library = Lticka, Cell = LED, View = layout
4. Click "Show Options".
5. Change the Stream Version to 3 (Do not touch other options).
6. Click "Translate" button.

   

vlsi> cd  ~/d
vlsi> mkdir  gds
vlsi> mv "file name of the streamdata"  ./gds/

Frame and IO

The following process should be carryed out by the project administrator. The top level desgn includes the frame of the chip, the IO buffers, the pads (NOTE), and core cells which are designed by the member of the project.

NOTE: A pad is a bare electrode in the frame of the chip which is passivated by the file having excellent chamical stability. The pads are used for bonding the lead of the package.

Schematic procedure:

1. Place the frame with the pad at the origin of the layout coordinate.
2. Place the IO buffers on the frame.
3. Place the core cells in a proper direction.
4. Wire the power line of the core cell, IO pins, the output and input of the buffer cells, and the pads.
5. Carry out the DRC for the whole chip.
6. Carry out the density rule check.
   The density rule, which is a constraint for the density of the the metal, gate, and active, is applied to the whole area of the chip. The semiconductor manifacturer does not accept the design data which does not pass the design rule check.
7. Export the stream dile of the chip.
8. Tape out of the stream file.
   The visual checking by all members participating in the project before submitting the data to the manufacturer is recommended.