1. HDL Code

   You can use the sample HDL code of LED controller. Copy the sample code into your work directory.

   vlsi> cd  ~/d
   vlsi> cp  -r  sample/verilog6  ICC
   vlsi> cd  ICC
   

   Block diagram of LED controller
   

   Verilog HDL files

   File name	Function
   div.v	(214-1) Divider
   pwm.v	4bit PWM
   blnk.v	Flicker circuit
   led.v	LED Controller
   tb_led.v	Testbench of led.v

2. Input file of logic simulator

   The file written about the list of the input files is read into the logic simulator. Create the text file completed the list of the verilogHDL files which you copied to the working directory (ICC), and save as "led.f".

   Contents of led.f

   tb_led.v led.v div.v pwm.v blnk.v

   NOTE: The tb_led.v is a testbench file (or the measurement circuit) to drive and monitor the behavior of the UUT (Unit Under Test). The other files are the source code files which define the function of each module. The testbench file should be at 1st line.

3. HDL simulation

   Execute following command lines to invoke Verilog-XL. The "setlic" is a script command to set the environment variables and the license server.

   vlsi> setlic 
         Choose the number of Cadence INCISIVE.
   vlsi> cd  ~/d/ICC
   vlsi> verilog  +gui  -s  -f  led.f &
   

   NOTE: Options of Verilog-XL command
   

   +gui	GUI mode
   -s	Suspend mode (The simulator temporary stop before starting the simulation and you can choose the signals to monitor.)
   -f	The name of the file written about the list of the input files

4. Monitoring the signals

   The verilog command with +gui option invoke SimVision. You can select the modules and variables to monitor. In this case, the instance "uut" is located under the testbench "tb_led". Click the module uut to find the list of the signals, and choose CLK, OUT, RST_B, WIDTH[3:0], dout, and pout.

   

   The block diagram of the HDL design is shown by clicking the icon of a block diagram on the toolbar. You may double-click to see the block diagram in the lower hierarchical level.

   

   Click the icon of a waveform on the toolbar to show the waveform vewer.

   

   

5. Starting the simulation

   Click the start button on the waveform viewer to start the simulation and the result is shown as a timing chart. If you want to see the waveform between the first and last, Click the "=" button. Confirm the time-modulated pulse width of pout. After the operation check, you can stop the simulation with the interrupt button on the right of the run button.

6. Exiting Verilog-XL

   Menu: File > Exit SimVision

1. Specifying the standard cell library

   Create the setup-file of the logic synthesizer in the working directory (ICC) and save as ".synopsys_dc.setup". This file specifies the path to the standard cell libraries.

   .synopsys_dc.setup

   set search_path "$search_path ../kyoto/synthesis/lib/" set target_library “ROHM18_FF.db ROHM18_WO_FF.db” set link_library "* ROHM18_FF.db ROHM18_WO_FF.db ROHM18_ADD.typ.db"

2. Description of the constraint condition

   Create the constraint file in the working directory (ICC) and save as "led.sdc".

   led.sdc

   create_clock -name CLK -period 2.0 -waveform {0 1.0} [get_port {CLK}] set_clock_uncertainty 0.1 -setup [get_port {CLK}] set_clock_uncertainty 0.1 -hold [get_port {CLK}]

   The constraint file is formatted with SDC (Synopsys Design Constraint Format). In this example, the clock is specified as follows.

   Clock signal name	CLK
   Period	2.0ns
   Delay time of rising edge and pulse width	0ns and 1.0ns, that is, Duty ratio = 50%.
   Jitter of the setup time	0.1ns
   Jitter of the hold time	0.1ns

   ---

   You can specify other constraints as follows. In this example, you do not use these descriptors.
   1. External input delay

      set_input_delay 0.5 -max -clock "CLK" {WIDTH} set_input_delay 0.2 -min -clock "CLK" {WIDTH}

      For the input port WIDTH[3:0],

      Reference clock name	CLK
      Maximum delay time	0.5ns
      Minimum delay time	0.2ns

      NOTE: The target circuit is synthesized without the setup time violation, even if the output of the previous stage is delayed.

      

   2. External output delay

      set_output_delay 0.5 -max -clock "CLK" {OUT} set_output_delay 0.2 -min -clock "CLK" {OUT}

      For the output port OUT,

      Reference clock name	CLK
      Maximum delay time	0.5ns
      Minimum delay time	0.2ns

      NOTE: The target circuit is synthesized without the setup time violation at the next clock edge, even if the subsequent stage requires the timing budget.

      

   3. Operating conditions
      • Driving strength of input signal

        set_drive 3 {CLK} set_drive 3 {RST_B}

        For the input ports CLK and RST_B,

        The output resistance of the previous stage is

        3kohm.

        NOTE: If drive = 0 (resistance = 0), the drive strength is infinite. The unit of the resistance depends on the definition of the standard cell library. If the target circuit is driven by the IO cell, you may specify the name of the name of the IO cell.

      • Capacitive load

        set_load -pin_load 0.01 {OUT} set_load -min -pin_load 0.01 {OUT}

        For the output port OUT,

        The load capacitance of output port is

        0.01 pF.

        NOTE: The unit of the capacitance depends on the definition of the standard cell library.

   ---

3. Logic synthesis

   Execute following command lines to invoke Design Vision (Design compiler in GUI mode)

   vlsi> cd  ~/d/ICC
   vlsi> setlic 
         Choose the number of Synopsys Synthesis.
   vlsi> cd  ~/d/ICC
   vlsi> design_vision (Don't use &)
   

   1. Menu: File > Read... or Folder button on the toolbar.
   2. Choose Format=VERILOG(v) and open all VerilogHDL files (led.v, div.v, blnk.v, pwm.v).
      NOTE: Click led.v first, then div.v, blnk.v, pwm.v with CTRL key.
   3. Menu: File > Link Design..., Confirm the library name (for example, ROHM18_FF.db) and click OK button.

      

   4. Set the top module of your design (LED) into the module name box on the toolbar.
   5. After choosing the top cell or sub-cell, You can see the block diagram of your design by clicking the icon of the blocks.
   6. Execute the command line for the he command prompt "design_vision>" to read the constraint file. NOTE: You have to choose the top cell on the toolbar before the execution of "read_sdc".

      design_vision> read_sdc  led.sdc
      

      You may directly execute the contents of the SDC file for the command prompt of "design_vision>", instead of "read_sdc".
   7. Menu: Attribute > Optimizing Constraints > Design Constraints..., and set "Max Area = 0". In this condition, the small area of the circuit is given the first priority in the optimization process.
      If the area has been assigned for the circuit, set the assigned area for the constraint.
   8. Menu: Design > Compile Design... and click the OK button to start the logic synthesis. You can use "ungroup" check box to flat the hierarchic structure. It takes a long time for the logic synthesis, but the better optimaiztion result is expected.

      

   9. You can see the synthesized circuit by clicking Menu: Select > Cells > Top Design and Menu: Schematic > New Schematic View.

4. Checking the report
   1. Menu: Design > Report Area
      The report of the used cells is shown.
   2. Menu: Timing > Report Timing Path...
      The report of the timing is shown. Check the slack (timing budget). If the slack is negative value, the timing constraint is violated, that is, the synthesized circuit may not work in the specified clock frequency.
   3. Toolbar: Click the icon of timer (Create Path Slack Histogram)
      You can see the histogram of the number of the interconnect associated with the critical path.
   4. Toolbar: Click another icon of timer (Create Endpoint Slack Histogram)
      You can see the histogram of the number of all interconnect

5. Saving the result
   1. Mane: File > Save As...
   2. Format = DDC, File Name = led.ddc
      The constraint condition and the synthesized result are saved in the DDC file.
   3. Execute following command line. This command generates a VerilogHDL netlist with the standard format which is required to read in some other CAD tool.

      design_vision> define_name_rules  verilog  -allowed "A-Z0-9_" 
      design_vision> change_names  -rule  verilog  -hierarchy 
      

   4. Menu: File > Save As...
   5. Format = VERILOG(v), Filename = led_syn.v
   6. Execute following command line to generate SDF file which includes the delay time information in the synthesized circuit. The SDF file can be used for the optimization of place and route process.

      design_vision> write_sdf  -version 1.0  led.sdf 
      

6. Exiting Design Vision
   1. Menu: File > Exit

You can check the timing error of the synthesized logic through the timing simulation. In the functional simulation, the propagation delay of the logic gate is excluded because the purpose of this simulation is a verification of the coding. On the other hand, the propagation delay of each logic gate is considered in the timing simulation, because the purpose of this simulation is the operation check of the synthesized logic. If the timing design is not critical, you can skip this process.

1. Create the list of the input files and save as "led_syn.f".

   Contents of led_syn.f

   tb_led.v led_syn.v -v ../kyoto/verilog/rohm18_typ.v

   NOTE: The cell library described with VerilogHDL can be specified with the option -v. "rohm18_typ.v" include the functions and the typical delay time of standard cells.

   The operation procedure of the timing simulation is similar to the functional simulation.

   vlsi> setlic 
         Choose the number of Cadence INCISIVE.
   vlsi> cd  ~/d/ICC
   vlsi> verilog  +gui  -s  -f  led_syn.f
   

   NOTE: Each bit is separately displayed in the timing chart. Choose the multiple bit by "CTRL + Click" and right-click. Then, choose "Create bus" in the pop-up menu to show the integer representation. You can also change the radix of the integer in the 2nd column in the timing chart window.