`timescale 1ns / 1ps

module tb_ddsm2_16_v;

	// Inputs
	reg [15:0] in;
	reg clk;
	reg rst;

	// Outputs
	wire out;

	// Half cycle of clock
    	parameter hf_cycle = 50;
	integer i, j;

	// Instantiate the Unit Under Test (UUT)
	ddsm2_16 uut (
		.in(in), 
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial begin
		// Initialize Inputs
		in = 16'h8000;
		//in = 16'hfff0;
		clk = 0;
		rst = 0;

		// Wait 100 ns for global reset to finish
		#(2*hf_cycle);
        
		// Add stimulus here
		rst = 1'b1;
		#(hf_cycle);
		
		for (j = 0; j < 16; j = j + 1) begin
			#(128*2*hf_cycle) in = in + 16'h1000;
		//	#(128*2*hf_cycle) in = in + 16'h0000;
		end
	end
		
	// Clock Generation
    	initial begin
        clk <= 1'b0;
        for (i = 0; i < 4300; i = i + 1)
            #(hf_cycle) clk <= ~clk;
        $finish;
    end
      
endmodule